There is a strong demand for supply at low prices of multilayer wiring substrates suitable for high-density mounting of semiconductor chips such as LSI's for use in not only industrial applications but also the wide field of consumer-oriented products, as with the recent trend of downsizing and high performance of electronic products. It is important for a multilayer wiring substrate of such kind to provide highly reliable electrical connections among wiring traces formed with fine pitches on a plurality of layers.
In the field of semiconductor interposers using many high-density wiring substrates, there is a substantial increase in number of connecting terminals of semiconductors due to the increase of signal and grounding terminals proportionate to the multifunctional trend of semiconductors. Since fine-pitch mounting of semiconductors is advancing continuously due to the need of mounting such semiconductors into packages of the conventional size, the requirement continues to exist for further fining of mounting pitches, especially for semiconductor interposers.
On the other hand, there is also advancement in the area of fine-pitch mounting between mother boards and ball grid arrays (BGA), in which terminal pitches of 0.5 mm or less are now used widely, and it is therefore the current situation that requires measures to deal with pitches as small as 0.25 mm.
As the terminal pitches decrease in this manner, it becomes inevitable that land areas for mounting BGA's also decrease. It is therefore necessary to provide wiring traces with a higher bonding strength per unit area in order to ensure the strength of wiring lands.
To fulfill such needs of the market, there exists a technique called an inner viahole connection method capable of making interlayer connections of any electrodes at any positions of wiring traces of multilayer wiring substrates, or multilayer resin substrates of an all-layer IVH structure, in place of the ordinary plated metal conductors on inner walls of through-holes, which has been the main current of interlayer connections of the conventional multilayer wiring substrates. This method can make connections possible among only the desired layers through a conductive material filled in viaholes of the multilayer wiring substrate, and achieve downsizing of the substrate and high-density mounting since it enables formation of the inner viaholes just under component lands. In addition, the method can reduce the stress imposed on inner viaholes, and attain stable electrical connections irrespective of dimensional changes due to thermal shocks, etc. since the electrical connections in the inner viaholes are made with conductive paste.
A multilayer wiring substrate manufactured by taking the steps illustrated in FIG. 8A to FIG. 8I has been proposed in the past as this type of multilayer resin substrate of all layer IVH structure.
For a start, shown in FIG. 8A is electrical insulation substrate 21, on which protective films 22 are bonded to both surfaces by a laminating process. It is then processed with a laser or the like to form through-holes 23 that penetrate through all of electrical insulation substrate 21 and protective films 22, as shown in FIG. 8B. Next, through-holes 23 are filled with electrically conductive paste 24, which serves as a conductive material, as shown in FIG. 8C. Protective films 22 are removed thereafter from both surfaces, and foil wiring members 25 are laid on both of the surfaces under this condition, to thus prepare the state shown in FIG. 8D.
Wiring members 25 are subjected to thermo-compression in the step shown in FIG. 8E to bond them with electrical insulation substrate 21. This process of thermo-compression hardens electrically conductive paste 24, and makes electrical connections between wiring members 25 and electrically conductive paste 24.
Next, wiring members 25 are patterned by an etching process to complete double-sided wiring substrate 26, as shown in FIG. 8F.
Following the above, electrical insulation substrates 27 having electrically conductive paste filled therein and formed by the same steps as illustrated in FIGS. 8A to 8D are laid together with wiring members 28 on both surfaces of double-sided wiring substrate 26, as shown in FIG. 8G.
Subsequently, wiring members 28 are subjected to thermo-compression in the step shown in FIG. 8H to bond them to electrical insulation substrate 27. Double-sided wiring substrate 26 and electrical insulation substrates 27 are also bonded at the same time in this step.
This process of thermo-compression hardens electrically conductive paste 29 in the same manner as in the step shown in FIG. 8E, and makes wiring members 28 and wiring traces 30 on the double-sided wiring substrate come into close contact to complete electrical connections between them.
Wiring members 28 on the outer layers are patterned next by the etching process to complete the multilayer wiring substrate shown in FIG. 8I. The multilayer wiring substrate shown here is an example of a four-layered substrate. The number of layers of the multilayer wiring substrate is not limited to four; rather, the number of layers can be increased by repeating the same steps. Japanese Patent Unexamined Publication, No. H06-268345 is one example of the prior art documents known to be related to the invention of this application.
Besides the above, Japanese Patent Unexamined Publication, No. 2000-68620 discloses a method of roughening interfaces between wiring members and electrically conductive pastes by abrasive machining such as sandblasting and jet scrubbing, as a technique for improving the electrical continuity via the through-holes in the multilayer wiring substrate.
In the case of patterning the wiring members by etching in the manner as described, it is necessary to control a width of wiring traces highly accurately by setting an etching time to the minimum required to form the fine wiring traces and to reduce excessive thinning of the wiring traces due to over-etching. In other words, it is essential to use a material having a smooth surface for the wiring members in order to reduce an amount of embedment into the electrical insulation substrate, which can result in variations of the etching time.
When the wiring members used have smooth surfaces, however, bonding to the electrical insulation substrate weakens. This gives rise to a problem that a strength of bonding of the wiring traces becomes deficient, thereby causing the wiring traces to come off at portions where mechanical stresses concentrate during mounting.
In addition, reduction in diameters of the through-holes for the purpose of fining wiring pitches inevitably results in decrease of contact areas and thus decrease in the number of electrical contacting points between the wiring traces and the electrically conductive pastes. Resultant contact conditions with conductive particles will have a considerable effect upon their electrical continuities. When surfaces of the wiring members are roughened into a finely and sharply pointed configuration for improvement of the bonding strength of the wiring traces, for instance, their contacting areas with the conductive particles decrease on the contrary, which also gives rise to another problem of degrading the electrical connections.